Inter-Integrated Circuit (I2C) Interface
Introduction
The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
I2C main features
I2C bus specification compatibility:
Slave and master modes
Multimaster capability
Standard-mode (up to 100 kHz)
Fast-mode (up to 400 kHz)
Fast-mode Plus (up to 1 MHz)
7-bit and 10-bit addressing mode
I2C functional description
I2C signals
I2C communications require two pins: Serial Clock (SCL) and Serial Data (SDA):
SCL (Serial Clock)
SCL is the bidirectional clock signal. When the device is in master mode, the device drives the SCL pin. When the device is in slave mode, the SCL pin is in input mode. Commonly, SCL is color-coded as green.
SDA (Serial Data)
SDA is the bidirectional data signal.
I2C operates in open-drain(OD) mode, which requires a pull-up resistor to the highest positive voltage supply on SCL and SDA pins. Commonly, SDA is color-coded as yellow.
I2C clock requirements
The Clock Generator generates an internal 4*Fscl clock enable signal which triggers all synchronous elements in the Bit Command Controller. It also handles clock stretching needed by some slaves.
Clock Prescaler Register
The prescaler value can only be changed when EN bit is disabled.
I2C Communication Flow
Normally, a standard communication consists of four parts:
START signal generation
Slave address transfer
Data transfer
STOP signal generation
START signal
When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal is defined as a high-to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new data transfer. A Repeated START is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. writing to device to reading from device) without releasing the bus.
The core generates a START signal when the STA bit in the Status Command Register (STAT_CMD) is set and the RD or WR bits are set. Depending on the current status of the SCL line, a START or Repeated START is generated.
Slave address transfer
The first byte of data transferred by the master immediately after the START signal is the slave address.
This is a seven-bit calling address followed by a R/W bit. The R/W bit signals the slave data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the nineth SCL clock cycle.
The core treats a Slave Address Transfer as any other write action. Store the slave device’s address in the Data Register (DATA) and set the WR bit in the Status Command Register (STAT_CMD). The core will then transfer the slave address on the bus.
Data transfer
Once successful slave addressing is achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the R/W bit sent by the master. Each transferred byte is followed by an acknowledge bit on the nineth SCL clock cycle.
If the slave signals a No Acknowledge, the master can generate a STOP signal to abort the data transfer or generate a repeated START signal and start a new transfer cycle.
If the master, as the receiving device, does not acknowledge the slave, the slave releases the SDA line for the master to generate a STOP or repeated START signal.
For writing data to a slave, store the data to transmit in the Data Register (DATA) and set the WR bit in the Status Command Register (STAT_CMD). For reading data from a slave, set the RD bit in the Status Command Register (STAT_CMD). During a transfer the core set the TIP flag, indicating that a Transfer is In Progress and the peripheral is busy. When the transfer is done the TIP flag is reset, the IF flag set and, when enabled, an interrupt is generated. The Data Register (DATA) contains valid data after the IF flag has been set. The user may issue a new write or read command when the TIP flag is reset.
STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal is defined as a low-to-high transition of SDA while SCL is high.
Mode of Operation
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a START condition and ends with a STOP condition. Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the general call address. The general call address detection can be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A ninth clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter.
Data Reception
generate start signal
write slave address + write bit
receive acknowledge from slave
write memory location
receive acknowledge from slave
generate repeated start signal
write slave address + read bit
receive acknowledge from slave
read byte from slave
write no acknowledge (NACK) to slave, indicating end of transfer
generate stop signal
Data Transfer
generate start command
write slave address + write bit
receive acknowledge from slave
write data
receive acknowledge from slave
generate stop command
I2C registers
This section gives a detailed description of the I2C registers.
The peripheral registers can be written in word, half-word or byte mode.
Prescaler low register (PRESCAL_LO)
Address offset: 0x00
Reset value: 0x0000_00FF
| Bits | Name | Description |
|---|---|---|
7:0 | PRESCAL_LO | Lower part of the prescaler value. These bits are set and cleared by software. |
Prescaler high register (PRESCAL_HI)
Address offset: 0x04
Reset value: 0x0000_00FF
| Bits | Name | Description |
|---|---|---|
7:0 | PRESCAL_HI | Higher part of the prescaler value. These bits are set and cleared by software. |
Control register (CTRL)
Address offset: 0x08
Reset value: 0x0000_0000
| Bits | Name | Description |
|---|---|---|
7 | EN | I2C core enable bit. These bits are set and cleared by software. 0: core disabled 1: core enabled |
6 | IEN | I2C interrupt enable bit. These bits are set and cleared by software. 0: interrupt disabled 1: interrupt enabled |
Data register (DATA)
Address offset: 0x0C
Reset value: 0x0000_0000
| Bits | Name | Description |
|---|---|---|
7:0 | DATA | Data field. When read, returns the last data received by I2C RX; when written, puts the value into I2C TX buffer. When used with I2C START condition, the LSB is I2C R/W mode bit. These bits are set and cleared by software. Note that writing and reading are operating on different fields. 0: write command 1: read command |
Status command register (STAT_CMD)
Address offset: 0x10
Reset value: 0x0000_0000
| Bits | Name | Description |
|---|---|---|
7 | RXACK / STA | Receive acknowledgment status / start bit. When read, return the received acknowledge status from the slave; when written, generate (repeated) start condition These bits are set by software, and set and cleared by hardware. When read: 0: acknowledge received (ACK) 1: no acknowledge received (NACK) When written: 0: do not generate START (no effect) 1: generate START |
6 | BUSY / STO | Busy / stop bit. When read, return the bus status; when written, generate stop condition These bits are set by software, and set and cleared by hardware. These bits are set and cleared by software and hardware. When read: 0: detected STOP condition 1: detected START condition When written: 0: do not generate STOP (no effect) 1: generate STOP |
5 | RD | Initiate a read from slave operation. When written: 0: do nothing 1: start a read operation |
4 | WR | Initiate a write to slave operation. When written: 0: do nothing 1: start a write operation |
3 | ACK | Send acknowledge bit When written: 0: do nothing 1: send acknowledge bit |
1 | TIP | Indicate if a transfer is in progress. When read: 0: transfer is complete 1: transfer in progress |
0 | IF | Indicate if an interrupt is pending Will cause a processor interrupt request if IEN bit is set When read: 0: transfer is complete 1: transfer in progress |
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