6. Chipyard Simulation

Simple RISCV tests can be found under $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/and can be run as:

bsub -I -XF -q ee194 make run-binary CONFIG=RocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

Open up the .out file generated by the assembly test you ran (in vcs/output) and answer the following questions:

6.1. How many cycles did the simulation take to complete?

6.2. What is the hexidecimal representation of the last instruction run by the CPU?

In summary, when we run something like:

bsub -I -XF -q ee194 make run-binary CONFIG=RocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

The first command will elaborate the design and create Verilog. This is done by converting the Chisel code, embedded in Scala, into a FIRRTL intermediate representation which is then run through the FIRRTL compiler to generate Verilog. Next it will run VCS to build a simulator out of the generated Verilog that can run RISC-V binaries. The second command will run the test specified by BINARY and output results as an .out file. This file will be emitted to the $chipyard/sims/vcs/output/ directory.

Many Chipyard Chisel-based design looks something like a Rocket core connected to some kind of "accelerator" (e.g. a DSP block like an FFT module). When building something like that, you would typically build your "accelerator" generator in Chisel, and unit test it using ChiselTesters. You can then write integration tests (eg. a baremetal C program) which can then be simulated with your Rocket Chip and "accelerator" block together to test end-to-end system functionality. Chipyard provides the infrastructure to help you do this for both VCS (Synopsys) and Verilator (open-source). The same infrastructure enables a few other applications as depicted below.

SW RTL Simulation: RTL-level simulation with VCS or Verilator. If you design anything with Chipyard, you should be running SW RTL simulation to test. Hammer VLSI flow: Tapeout a custom config in some process technology. FPGA prototyping: Fast, non-deterministic prototypes (we won't be doing this in this class). FireSim: Fast, accurate FPGA-accelerated simulations (we won't be using this in this class, but if you're curious about FireSim, check out its documentation here and feel free to reach out to a TA to learn more).

In summary...

Configs: Describe parameterization of a multi-generator SoC. Generators: Flexible, reusable library of open-source Chisel generators (and Verilog too). IOBinders/HarnessBinders: Enable configuring IO strategy and Harness features. FIRRTL Passes: Structured mechanism for supporting multiple flows. Target flows: Different use-cases for different types of users.

Next Step

page7. Design, Test and Integration