Running Chipyard RTL Simulation - Ubuntu or BWRC
In this tutorial, we will simulate a simple SoC and make it print "Hello World".
Step 1. Preparing the Environment
On Ubuntu, we will use the open-source Verilator to simulate.
We don't need to do anything special to use Verilator. Just remember to source the env.sh script.
source $chipyard/env.sh
On BWRC machine, we need to source the VCS simulator path. This can be done by executing the following commands.
export VCS_HOME=/tools/synopsys/vcs/S-2021.09-SP1-1/
export VERDI_HOME=/tools/synopsys/verdi/S-2021.09-SP1-1/
export VCS_64=1
export PATH=$VCS_HOME/bin:$VERDI_HOME/bin:$PATH
Alternatively, run the following all-in-one script
source /tools/C/chiyufeng/documents/vcs_env.sh
If running into license issues, try running the following command
source /tools/flexlm/flexlm.sh
If running into JDK_HOME issue(JDK/lib/tools.jar not found), try the following command
export JDK_HOME=/usr/lib/jvm/java-1.8.0/
Step 2. Running the Simulation
To build simulation code:
cd $chipyard/tests/
make
Then, we go to the corresponding simulator folder and run the simulation.
cd $chipyard/sims/verilator/
make run-binary CONFIG=ExampleChipConfig BINARY=../../tests/hello.riscv
cd $chipyard/sims/vcs/
bsub -q ee194 -Is -XF make run-binary CONFIG=ExampleChipConfig BINARY=../../tests/hello.riscv
To run simulation with a program:
bsub -q ee194 -Is -XF make run-binary CONFIG=BearlyConfig BINARY=../../tests/hello.riscv
To run simulation with a program, and generate waveform:
bsub -q ee194 -Is -XF make run-binary-debug CONFIG=BearlyConfig BINARY=../../tests/hello.riscv timeout_cycles=10000
timeout_cycles can be set to a small value to make the waveform dump process faster.
Step 3. Examine Waveform
Launch verdi to examine the waveform
bsub -q ee194 -Is -XF verdi
b
c
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