3. Chipyard Repo Tour

Note: You will mostly be working out of the generators/ (for designs), sims/vcs/ (for RTL simulations) and vlsi/ (for physical design) directories. However, we will still give a general repo tour to get you familiar with Chipyard as a whole.

A partial view of the chipyard directory structure is shown below.

 chipyard/
  generators/ <------- library of Chisel generators
    chipyard/
    rocket-chip/
    boom/
    testchipip/
  fpga/
  sims/ <------------- utilities for simulating SoCs
    vcs/
    verilator/
    firesim/
  software/
  tests/ <------------ Baremetal tests
  toolchains/ <------- RISC-V Toolchain, including baremetal tests
  vlsi/ <------------- HAMMER VLSI Flow

You may have noticed while initializing your Chipyard repo that there are many submodules. Chipyard is built to allow the designer to generate complex configurations from different projects including the in-order Rocket Chip core, the out-of-order BOOM core, the systolic array matrix multiply accelerator Gemmini, and many other components needed to build a chip. Thankfully, Chipyard has some great documentation, which can be found here.

You can find each of these projects in the $chipyard/generators/ directory. All of these modules are built as generators (a core driving point of using Chisel), which means that each piece is parameterized and can be fit together with some of the functionality in Rocket Chip (check out the TileLink and Diplomacy references in the Chipyard documentation).

The generators that you will see used most frequently are rocket-chip, testchipip, and chipyard. Not only does the rocket-chip generator contain the in-order Rocket core, it also contains the tile code, TileLink code, L1 cache code, and subsystem code. The testchipip generator contains chip peripheral/IO components and other useful SoC building components. The chipyard generator contains the SoC configuration code and the top-level code for generating and simulating the SoC (ChipTop and TestHarness).

SoC Architecture

Location on SoC	Component and Description
	Tiles A tile is the basic unit of replication of a core and its associated hardware Each tile contains a RISC-V core and can contain additional hardware such as private caches, page table walker, TileBus (specified using configs) Several varieties of cores (Rocket, BOOM, Sodor, CVA-6 (Ariane), Ibex supported) Contains APIs for integrating your custom RISC-V core
	RoCC Accelerators Tightly-coupled accelerator interface Attach custom accelerators to Rocket or BOOM cores Example: GEMMINI accelerator
	MMIO Accelerators Controlled by memory-mapped IO registers Supports direct memory access (DMA) to the memory system Examples: Nvidia NVDLA accelerator & FFT accelerator generator
	Chip Interconnect TileLink Standard TileLink is an open-source chip-scale interconnect standard (i.e., a protocol defining the communication interface between different modules on a chip) Comparable to industry-standard protocols such as AXI/ACE Supports multi-core, accelerators, peripherals, DMA, etc. Interconnect IP in Chipyard Library of TileLink RTL generators provided in RocketChip RTL generators for crossbar-based buses Width-adapters, clock-crossings, etc. Adapters to AXI4, APB Constellation A parameterized Chisel generator for SoC interconnects Protocol-independent transport layer Supports TileLink, AXI-4 Highly parameterized Deadlock-freedom Virtual-channel wormhole-routing
	Shared Memory Open-source L2 cache that communicates over TileLink (developed by SiFive) Directory-based coherence with MOESI-like protocol Configurable capacity/banking Supports broadcast-based coherence in no-L2 systems Supports incoherent memory systems DRAM AXI-4 DRAM interface to external memory controller Interfaces to DRAM simulators such as DRAMSim/FASED
	Peripherals and IO Chipyard Peripheral User Manual put together by Yufeng Chi who took the Sp22 iteration of this class. This document is a living document, so feel to add comments on sections that you don't understand/woud like to see added. Open-source RocketChip + SiFive blocks: Interrupt controllers JTAG, Debug module, BootROM UART, GPIOs, SPI, I2C, PWM, etc. TestChipIP: useful IP for test chips Clock-management devices SerDes Scratchpads Documentation for the peripheral devices can be found here

Next Step

page4. Config Exercise