Misc FPGA Issues

Default SPI Frames

default SPI frame is MSB first, SCLK is default low, and data is latched on SCLK rising edge (SPI mode 0)

Size should be 2^2 for either, FESVR is not very thoroughly tested on 32 bit systems.

VCU118

DO NOT PRESS `PROGRAM` BUTTON!!! This will erase the image on FPGA