Introduction to Chipyard
Chipyard is an integrated design, simulation, and implementation framework for open source hardware development developed here at UC Berkeley. It is open-sourced online and is based on the Chisel and FIRRTL hardware description libraries, as well as the Rocket Chip SoC generation ecosystem. It brings together much of the work on hardware design methodology from Berkeley over the last decade as well as useful tools into a single repository that guarantees version compatibility between the projects it submodules.
A designer can use Chipyard to build, test, and tapeout (manufacture) a RISC-V-based SoC. This includes RTL development integrated with Rocket Chip, cloud FPGA-accelerated simulation with FireSim, and physical design with the Hammer framework.
Chisel is the primary hardware description language used at Berkeley. It is a domain-specific language built on top of Scala. Thus, it provides designers with the power of a modern programming language to write complex, parameterizable circuit generators that can be compiled into synthesizable Verilog. You will be writing a few lines of basic Chisel code in this lab, however, it is NOT the focus of this lab. This lab aims to familarize you with the Chipyard framework as a whole.
Here are some resources to learn more about Chisel:
Students interested in designing accelerators and other IP blocks are especially encouraged to consult these resources.
We will be developing our SoC using Chipyard as the base framework. There is a lot in Chipyard so we will only be able to explore a part of it in this tutorial, but hopefully you will get a brief sense of its capabilities.
In particular, the tutorial series provides a brief overview of Chipyard's diverse features and then guides you through designing, verifying, and incorporating an accelerator into an SoC (via RoCC and MMIO interfaces), and finally simulating the SoC in both RTL simulation and on a real FPGA.
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