5. Elaborating Chisel

Let's run some commands!

So far, we have been working on the login servers. From this point on, we will be running some more compute-intensive commands on the compute servers. Prepend all compute heavy commands (everything ran in the vlsi/ directory & sims/ directories) with bsub -Is -q ee194. This submits the job to a special queue of compute servers for the class so we don't crash the login servers and mess up ongoing research work (or cause each other to lose valuable work :)).

We'll be running the CONFIG=RocketConfig config (the -j16 executes the run with more threads). All commands should be run in $chipyard/sims/vcs.

Run

cd $chipyard/sims/vcs
bsub -I -XF -q ee194 make CONFIG=RocketConfig -j16

NOTE: You may need to ssh with X-forwarding to get this command to run correctly. Please see the below troubleshooting section for fixes in the case that this command doesn't work.

pageTroubleshooting / FAQ

Note:

Remember to do

source /tools/C/ee290/mambaforge/bin/activate
source /tools/C/ee290/vcs_env.sh

FIRRTL is used to translate Chisel source files into another representation--in this case, Verilog. Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. Once the transformations are done, a Verilog file is emitted and the build process is done. You can think of FIRRTL as an HDL version of LLVM if you are familar with LLVM (depicted below).

After the run is done, check the $chipyard/sims/vcs/generated-src folder. Find the directory of the config that you ran and you should see the following files:

• gen-collateral/: generated verilog files

• *.dts: device tree string

• *.memmap.json: memory map

The verilog source files are a useful debugging tool, as they are the files that are actually simulated. A specific usecase is to use the verilog files to see if any modules were optimized out during elaboration.

Answer the following questions:

5.1. Looking only at the emitted files, how many bytes are in a block for the L1 DCache? How many sets are in the L1 DCache?

5.2. Looking only at the emitted files, how many bytes are in a block for the L1 ICache? How many sets are in the L1 ICache?

5.3. Try to find the top-level verilog modules that correspond to the ICache/DCache. Inside which verilog module is the DCache instantiated? Inside which verilog module is the ICache instantiated?

Next Step

page6. Chipyard Simulation